The increasing operating speeds and computing power of microelectronic devices have recently given rise to the need for an increase in the complexity and functionality of the semiconductor structures that are used as the starting substrates in these microelectronic devices. Such “virtual substrates” based on silicon and germanium provide a platform for new generations of very large scale integration (“VLSI”) devices that exhibit enhanced performance when compared to devices fabricated on bulk Si substrates. Specifically, new technological advances enable formation of heterostructures using silicon-germanium alloys (hereinafter referred to as “SiGe” or “Si1-xGex”) to further increase performance of the semiconductor devices by changing the atomic structure of Si to increase electron and hole mobility.
The important component of a SiGe virtual substrate is a layer of SiGe heterostructure that has been relaxed to its equilibrium lattice constant (i.e., one that is larger than that of Si). This relaxed SiGe layer can be directly applied to a Si substrate (e.g., by wafer bonding or direct epitaxy), or atop a relaxed graded SiGe buffer layer in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer. The SiGe virtual substrate may also incorporate buried insulating layers, in the manner of a silicon-on-insulator (SOI) wafer. To fabricate high-performance devices on these platforms, thin strained layers of semiconductors, such as Si, Ge, or SiGe, are grown on the relaxed SiGe virtual substrates. The resulting biaxial tensile or compressive strain alters the carrier mobilities in the layers, enabling the fabrication of high-speed and/or low-power-consumption devices. The percentage of Ge in SiGe and the method of deposition can have a dramatic effect on the characteristics of the strained Si layer. U.S. Pat. No. 5,442,205, “Semiconductor Heterostructure Devices with Strained Semiconductor Layers,” incorporated herein by reference, describes one such method of producing a strained Si device structure.
An approach to epitaxially growing a relaxed SiGe layer on bulk Si is discussed in International Application Publication No. WO 01/22482, entitled “Method of Producing Relaxed Silicon Germanium Layers” and incorporated herein by reference. The method includes providing a monocrystalline Si substrate, and then epitaxially growing a graded Si1-xGex layer with increasing Ge concentration at a gradient of less than 25% Ge per micrometer to a final Ge composition in the range of 0.1≦x≦1, using a source gas of GexHyCz for the Ge component, on the Si substrate at a temperature in excess of 850° C., and then epitaxially growing a semiconductor material on the graded layer.
Another method of epitaxially growing a relaxed SiGe layer on bulk Si is discussed in a paper entitled, “Low Energy plasma enhanced chemical vapor deposition,” by M. Kummer et al. (Mat. Sci.  Eng. B89, 2002, pp. 288-95) and incorporated herein by reference, in which a method of low-energy plasma-enhanced chemical vapor deposition (LEPECVD) is disclosed. This method allows the formation of a SiGe layer on bulk Si at high growth rates (0.6 μm per minute) and low temperatures (500-750° C.).
To grow a high-quality, thin, epitaxial strained Si layer on a graded SiGe layer, the SiGe layer is, preferably, planarized or smoothed to reduce the surface roughness in the final strained Si substrate. Current methods of chemical mechanical polishing (“CMP”) are typically used to decrease roughness and improve the planarity of surfaces in semiconductor fabrication processes. U.S. Pat. No. 6,107,653, “Controlling Threading Dislocations in Ge on Si Using Graded GeSi Layers and Planarization,” incorporated herein by reference, describes how planarization can be used to improve the quality of SiGe graded layers.
One technique suitable for fabricating strained Si wafers can include the following steps:                1. Providing a silicon substrate that has been edge-polished;        2. Epitaxially depositing a relaxed graded SiGe buffer layer to a final Ge composition on the silicon substrate;        3. Epitaxially depositing a relaxed Si1-xGex cap layer having a constant composition on the graded SiGe buffer layer;        4. Planarizing or smoothing the Si1-xGex cap layer and/or the relaxed graded SiGe buffer layer by, e.g., CMP;        5. Epitaxially depositing a relaxed Si1-xGex regrowth layer having a constant composition on the planarized surface of the Si1-xGex cap layer; and        6. Epitaxially depositing a strained silicon layer on the Si1-xGex regrowth layer.        
By introducing strain gradually over a series of low lattice mismatch interfaces, compositionally graded layers, as recited in step 2 above, offer a viable route toward integration of heavily lattice-mismatched monocrystalline semiconductor layers on a common substrate, offering a route towards increased functionality through monolithic integration.
The lattice constant of SiGe is larger than that of Si, and is a direct function of the amount of Ge in the SiGe alloy. As the SiGe graded buffer layer is epitaxially deposited, it will initially be strained to match the in-plane lattice constant of the underlying silicon substrate. However, above a certain critical thickness, the SiGe graded buffer layer will relax to its inherently larger lattice constant. The process of relaxation occurs through the formation of misfit dislocations at the interface between two lattice-mismatched layers, e.g., a Si substrate and a SiGe epitaxial layer (epilayer). Because dislocations cannot terminate inside a crystal, misfit dislocations have vertical dislocation segments at each end (termed “threading dislocations”), that may rise through the crystal to reach a top surface of the wafer. Both misfit and threading dislocations have stress fields associated with them. As explained by Eugene Fitzgerald et al., Journal of Vacuum Science and Technology B, Vol. 10, No. 4, 1992 (hereafter, “Fitzgerald et al.”), incorporated herein by reference, the stress field associated with the network of misfit dislocations affects the localized epitaxial growth rate at the surface of the crystal. This variation in growth rates may result in a surface cross-hatch on lattice-mismatched, relaxed graded SiGe buffer layers grown on Si.
The deposition of the relaxed graded SiGe buffer layer enables engineering of the in-plane lattice constant of the SiGe cap layer (and therefore the amount of strain in the strained silicon layer), while reducing the introduction of dislocations. For example, compositionally graded SiGe layers grown on Si(001) offer at least a three-order-of-magnitude reduction in threading dislocation density (TDD) when compared to direct deposition of relaxed SiGe layers without such buffer layer, and the resulting relaxed SiGe layer acts as a “virtual substrate” for high mobility strained channels (e.g. strained Si). The stress field associated with misfit dislocations under certain conditions, however, may cause formation of linear agglomerations of threading dislocations, termed a “dislocation pile-up.”
A dislocation pile-up is generally defined as an area comprising at least three threading dislocations, with a threading dislocation density greater than 5×106/cm2, and with threading dislocations substantially aligned along a slip direction such that the linear density of dislocations within the pile-up and along a slip direction is greater than 2000/cm. For example, the slip directions in SiGe materials are in-plane <110> directions.
Numerous theories attempt to explain the nucleation of misfit dislocations regarding where they are formed in the crystal and by what process. These theories include formation at pre-existing substrate dislocations; heterogeneous formation at defects; and homogeneous formation, i.e., formation in defect-free, perfect crystal regions. As explained by Eugene Fitzgerald in an article published in Materials Science Reports, Vol. 7, No. 3, 1991 and incorporated herein by reference, however, the activation energy for homogeneous dislocation formation is so high that it is unlikely to occur. The most likely source of misfit dislocations in the crystal is heterogeneous nucleation at defects.
Thus, dislocation pile-ups can form through a variety of mechanisms, including heterogeneous nucleation from particles, nucleation from wafer edges, dislocation blocking via interactions with surface roughness (especially deep troughs in the characteristic crosshatch pattern) and buried dislocation strain fields, or untraceable nucleation events during growth of thick compositionally graded buffer layers.
As described in the article by Srikanth Samavedam et al. (published in Journal of Applied Physics, Vol. 81, No. 7, 1997, and incorporated herein by reference), a high density of misfit dislocations in a particular region of a crystal will result in that region having a high localized stress field. This stress field may have two effects. First, it may present a barrier to the motion of other threading dislocations attempting to glide past the misfits. This pinning or trapping of threading dislocations due to the high stress field of other misfit dislocations is known as work hardening. Second, the high stress field may strongly reduce the local epitaxial growth rate in that region, resulting in a deeper trough in the surface morphology in comparison to the rest of the surface crosshatch. This deep trough in the surface morphology may also pin threading dislocations attempting to glide past the region of high misfit dislocation density (MDD). This cycle may perpetuate itself and result in a linear region with a high density of trapped threading dislocations, i.e., a dislocation pile-up.
Thus, while the graded buffet approach has demonstrated considerable reduction of global threading dislocation density, the stress field associated with misfit dislocations under certain conditions may cause dislocation pile-up defects in the semiconductor heterostructure. Regardless of the specific mechanism behind pile-up formation, a high localized TDD present in dislocation pile-ups has a potentially devastating impact on the yield of devices formed in these regions and may render these devices unusable. Inhibiting the formation of dislocation pile-ups is, therefore, desirable.